The present invention relates to a level conversion circuit for shifting a voltage level of an input signal and outputting the resulting signal, and more particularly, to a level conversion circuit that includes a bias circuit for generating a bias potential.
A semiconductor integrated circuit device (LSI), which uses a plurality of power supplies, includes a level conversion circuit for connecting circuits that correspond to different power supply voltages. Such level conversion circuits for connecting circuits corresponding to different power supply voltages include a voltage increasing level conversion circuit and a voltage decreasing level conversion circuit. The voltage increasing level conversion circuit converts a signal of a low power supply voltage circuit into a signal of a high power supply voltage circuit. The voltage decreasing level conversion circuit converts a signal of a high power supply voltage circuit into a signal of a low power supply voltage circuit. The voltage increasing level conversion circuit needs to have the function of amplifying the voltage of a signal. Thus, the voltage increasing level conversion circuit tends to have a longer delay time and consumes greater power than the voltage decreasing level conversion circuit. There is a demand for reducing the delay time and power consumption of level conversion circuits.
For semiconductor integrated circuit devices in recent years, the degree of integration of their digital circuits has been improved along with miniaturization of their integrated circuits. To improve reliability and reduce power consumption of semiconductor integrated circuit devices, their digital circuits tend to use a lower power supply voltage. For example, an integrated circuit manufactured with 0.35 um technology uses a power supply voltage of 3.3 V, and an integrated circuit manufactured with 0.18 um technology uses a power supply voltage of 1.8 V. For semiconductor integrated circuit devices used in controllers of automobiles, there still is a demand for using a power supply voltage of 5 V, which is conventionally used, in their interface circuits. To meet this demand, a large number of presently manufactured LSIs include both an interface circuit operable at a conventional power supply voltage (e.g., 5 V) and an internal circuit operable at a power supply voltage lower than the power supply voltage of the interface circuit. Such LSIs include a level conversion circuit for connecting circuits that operate at different power supply voltages and shifting voltage levels.
Such an LSI that includes a level conversion circuit may not necessarily be an LSI to which a plurality of external power supplies with different voltages are connected. For example, a dynamic RAM (DRAM) or a flash electrically erasable programmable ROM (EEPROM) also uses a plurality of different power supply voltages. To be specific, an internal voltage increasing circuit may generate a voltage higher than an externally provided power supply voltage. This results in a plurality of different power supply voltages being used. Alternatively, an internal voltage decreasing circuit may generate an internal voltage lower than an externally provided power supply voltage. This results in a plurality of different power supply voltages being used.
Japanese Laid-Open Patent Publication Nos. 6-204850 (hereafter referred to as document 1), 2003-101405 (document 2), 2001-351393 (document 3), 2002-190731 (document 4), 2003-60496 (document 5), 2002-198800 (document 6), 2001-274675 (document 7), 9-7371 (document 8), and 6-37624 (document 9) disclose examples of level conversion circuits. A level conversion circuit may also be referred to as a level shift circuit or a level shifter circuit.
FIGS. 1 and 2 show typical conventional level conversion circuits. FIG. 1 shows a level conversion circuit 1, which is disclosed in document 1. FIG. 2 shows a level conversion circuit 2, which is disclosed in document 2.
The following first describes the level conversion circuit 1 of FIG. 1. The level conversion circuit 1 includes high voltage capacity PMOS (P-channel metal oxide semiconductor) transistors PH1 and PH2, high voltage capacity NMOS (N-channel metal oxide semiconductor) transistors NH1 and NH2, low voltage capacity PMOS transistors PL1 and PL2, and low voltage capacity NMOS transistors NL1 and NL2. In FIG. 1, symbols representing the high voltage capacity MOS transistors are circled to differentiate them from the low voltage capacity MOS transistors. In the other drawings in this specification, too, symbols representing high voltage capacity MOS transistors are circled.
The drain of the high voltage capacity NMOS transistor NH1 is connected to the drain of the high voltage capacity PMOS transistor PH1 and to the gate of the high voltage capacity PMOS transistor PH2. The source of the high voltage capacity NMOS transistor NH1 is connected to the ground. The drain of the high voltage capacity NMOS transistor NH2 is connected to the drain of the high voltage capacity PMOS transistor PH2 and to the gate of the high voltage capacity PMOS transistor PH1. The source of the high voltage capacity NMOS transistor NH2 is connected to the ground. The source of each of the PMOS transistors PH1 and PH2 is provided with a power supply voltage Vpp, which is for a high voltage circuit unit.
The low voltage capacity PMOS transistor PL1 and the low voltage capacity NMOS transistor NL1 form an inverter circuit 3. The low voltage capacity PMOS transistor PL2 and the low voltage capacity NMOS transistor NL2 form an inverter circuit 4. An input signal IN is provided to the inverter circuit 3. An output node N10 of the inverter circuit 3 (a connecting point of the MOS transistors PL1 and PL2) is connected to the inverter circuit 4 (the gate of each of the MOS transistors PL2 and NL2). Each of the inverter circuits 3 and 4 is provided with and operated at a power supply voltage Vdd, which is for a digital circuit.
The output node N10 of the inverter circuit 3 is connected to the gate of the high voltage capacity NMOS transistor NH1. An output node N11 of the inverter circuit 4 is connected to the gate of the high voltage capacity NMOS transistor NH2. An output signal OUT is output from a connecting point of the PMOS transistor PH2 and the NMOS transistor NH2.
As one example, the power supply voltage Vdd for a digital circuit may be 1.8 V and the power supply voltage Vpp for a high voltage circuit unit may be 5 V. In this case, the level conversion circuit 1 of FIG. 1 converts an input signal IN having a signal amplitude of 1.8 V into an output signal OUT having a signal amplitude of 5 V.
To be specific, when the input signal IN is at a high (H) level (a potential level of 1.8 V), the output node N10 of the inverter circuit 3 is set at a low (L) level (a potential level of 0 V), and the output node N11 of the inverter circuit 4 is set at an H level. With the output node N10 of the inverter circuit 3 being at the L level, the NMOS transistor NH1 is turned off. With the output node N11 of the inverter circuit 4 being at the H level, the NMOS transistor NH2 is turned on. When the NMOS transistor NH2 is turned on, the output signal OUT is set at the L level. Here, with the PMOS transistor PH2 being off, no stationary current flows through the circuit.
When the input signal IN is at a L level, the output node N10 of the inverter circuit 3 is set at a H level, and the output node N11 of the inverter circuit 4 is set at a L level. Thus, the NMOS transistor NH1 is turned on, and the NMOS transistor NH2 is turned off. With the NMOS transistor NH1 being on, a node N20 between the PMOS transistor PH1 and the NMOS transistor NH1 is set at a L level, and the PMOS transistor PH2 is turned on. With the PMOS transistor PH2 being on and the NMOS transistor NH2 being off, the output signal OUT is set at a H level. Here, with the NMOS transistor NH2 being off, no stationary current flows through the circuit.
The signal amplitude of the node N20 and the signal amplitude of the output signal OUT are set at the power supply voltage Vpp, i.e., at 5 V, which is a relatively high voltage. The power supply voltage Vpp of as high as 5 V is applied to circuit components around the node N20 and to circuit components around the output node of the output signal OUT. This means that the MOS transistors PH1, PH2, NH1, and NH2 need to be high voltage capacity transistors. Typically, the voltage capacity of a MOS transistor is increased by increasing the thickness of its gate oxide. To suppress the short-channel effect caused by an increased thickness of its gate oxide, and to improve its drain voltage capacity, a MOS transistor is required to have a long channel.
The level conversion circuit 1 described above is realized by a simple circuit structure and allows no stationary current to flow through the circuit. As such, the level conversion circuit 1 is widely used.
The following describes the level conversion circuit 2 of FIG. 2. In FIG. 2, components that are the same as the corresponding components of the level conversion circuit 1 of FIG. 1 are given the same reference numerals as those components. The level conversion circuit 2 includes a bias circuit 6, in addition to MOS transistors PH1, PH2, NH1, NH2, PL1, PL2, NL1, and NL2. A bias potential NB generated in the bias circuit 6 is provided to the gate of each of the high voltage capacity NMOS transistors NH1 and NH2. The source of the high voltage capacity NMOS transistor NH1 is connected to the output node N10 of the inverter circuit 3. The source of the high voltage capacity NMOS transistor NH2 is connected to the output node N11 of the inverter circuit 4.
The bias circuit 6 includes a resistor R2 and a high voltage capacity PMOS transistor PH5. The source of the PMOS transistor PH5 is provided with a power supply voltage Vpp, which is for a high voltage circuit unit, via the resistor R2. The gate of the PMOS transistor PH5 is provided with a power supply voltage Vdd, which is for a digital circuit. The drain of the PMOS transistor PH5 is connected to the ground.
The power supply voltage Vdd for a digital circuit is 1.8 V. The power supply voltage Vpp for a high voltage circuit unit is 5 V. The level conversion circuit 2 converts an input signal IN having a signal amplitude of 1.8 V into an output signal OUT having a signal amplitude of 5 V. The bias potential NB generated in the bias circuit 6 is higher than the power supply voltage Vdd by substantially a threshold voltage Vth of the PMOS transistor PH5 (NB=Vdd+Vth). The resistor R2 of the bias circuit 6 functions as a current source of a source follower circuit.
To be specific, when the input signal IN is at a H level (1.8 V), the output node N10 of the inverter circuit 3 is set at a L level (0 V), and the output node N11 of the inverter circuit 4 is set at a H level (1.8 V). As one example, the bias potential NB of the bias circuit 6 may be higher than the power supply voltage Vdd by the threshold voltage (e.g., 0.6 V), i.e., the bias potential NB may be 2.4 V (1.8+0.6 V). In this case, the node N10 is at a L level (0 V), and the bias potential NB is 2.4 V. Thus, the NMOS transistor NH1 is turned on (conducting state). Also, the node N11 is at a H level (1.8 V), and the bias potential NB is 2.4 V. Thus, only a voltage of 0.6 V is applied between the gate and source of the NMOS transistor NH2. The NMOS transistor NH2 is turned off (non-conducting state).
Here, with the NMOS transistor NH1 being on, the node N20 is set at a L level, and the PMOS transistor PH2 is turned on. With the PMOS transistor PH2 being on and the NMOS transistor NH2 being off, the output signal OUT is set at a H level. Here, with the NMOS transistor NH2 being off, no stationary current flows through the circuit.
When the input signal IN is at a L level, the output node N10 of the inverter circuit 3 is set at a H level, and the output node N11 of the inverter circuit 4 is set at a L level. In this case, the node N10 is at a H level (1.8 V) and the bias potential NB is 2.4 V. Thus, only a voltage of 0.6 V is applied between the gate and source of the NMOS transistor NH1. The NMOS transistor NH1 is turned off. Also, the node N111 is set at a L level (0 V), and the bias potential NB is 2.4 V. Thus, the NMOS transistor NH2 is turned on. The output signal OUT is set at a L level. Here, the PMOS transistor PH1 is turned on and the NMOS transistor NH1 is turned off, so that the node N20 is set at a H level (5 V). With the node N20 being at a H level, the PMOS transistor PH2 is turned off. Thus, no stationary current flows through the circuit.
In the level conversion circuit 2, the signal amplitude of the nodes N10 and N20 is limited within a range of 0 to 1.8 V. This means that a voltage equal to or greater than the power supply voltage Vdd for a digital circuit is never applied to the low voltage capacity MOS transistors PL1, PL2, NL1, and NL2. The bias potential is higher than the power supply voltage Vdd by substantially the threshold voltage Vth (i.e., the bias voltage is 2.4 V). This increases the gate-source voltage when the NMOS transistors NH1 and NH2 are turned on, and the level conversion circuit 2 realizes high-speed operation.
As described above, the level conversion circuit 2 is formed by adding the bias circuit 6 and improving the circuit connection of the level conversion circuit 1 of FIG. 1. The level conversion circuit 2 with the above-described structure operates at high speed while maintaining high bias reliability. Further, the level conversion circuit 2 allows no stationary current to flow through the circuit.